1. Field of the Invention
The present invention relates to a semiconductor device with a dual-damascene gate and a method of manufacturing the semiconductor device, and more particularly, to a semiconductor device having a dual-damascene gate capable of miniaturizing a gate pattern.
2. Description of the Related Art
Hereinafter, a related art method of manufacturing a semiconductor device having a gate will be schematically described with reference to FIGS. 1A to 1G.
FIGS. 1A to 1G are flowcharts showing the related art method of manufacturing a semiconductor device having a gate.
In general, in the related art method of manufacturing the semiconductor device having a gate, a pad oxide film or a gate oxide film 12 is formed on a semiconductor substrate or a silicon wafer 11, as shown in FIG. 1A. As shown in FIG. 1B, an N+ polysilicon layer 13 is deposited. As shown in FIG. 1C, a polysilicon layer gate 13′ is formed by a photolithography process. Lightly doped drain (LDD) regions 14a and 14b are formed by implanting impurities on an active region where source/drain regions are formed.
As shown in FIG. 1D, the gate oxide film 12 on the LDD regions 14a and 14b is removed. An insulating film, for example a nitride film, is deposited. A sidewall nitride film 15 is formed on a sidewall of the polysilicon gate 13′ by etching the nitride film.
As shown in FIG. 1E, highly-concentrated impurities are implanted in the source/drain active regions to form source/drain regions 16a and 16b. 
As shown FIG. 1F, titanium (Ti) is deposited by a sputtering method to form a Ti film 17.
As shown in FIG. 1G, a Ti silicide 17′ is formed by reacting Ti ions of the Ti film with Si ions. The Ti silicide film 17′ is selectively removed using a wet etchant from a portion of the Ti film 17 where the Ti ions do not react with the Si ions.
However, there is problem in that, in a related art gate profile forming method using patterning and dry etching processes, it is difficult to control a critical dimension (CD) of a gate and effectively implement the gate profile as the design size is reduced with improvement in a semiconductor technology.